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JOGM: A CMOS cell layout style using jogged transistor gates

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1 Author(s)
Hindmarsh, R.D. ; Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany

A new width minimizing layout style called jogged gate matrix (JOGM) for CMOS cells is described. The traditional gate matrix layout style is modified by inserting 45° jogs into transistor gates. Thus, JOGM improves CMOS cell width by 23% to 31% in comparison to traditional gate matrix layout. An approach for automatic layout generation is suggested

Published in:

Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European

Date of Conference:

20-24 Sep 1993