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Dynamic variable reordering for BDD minimization

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4 Author(s)
Felt, E. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; York, G. ; Brayton, R. ; Sangiovanni-Vincentelli, A.

Binary Decision Diagrams (BDDs) are a data structure frequently used to represent complex Boolean functions in formal verification algorithms. An efficient heuristic algorithm for dynamically reducing the size of large reduced ordered BDDs by optimally reordering small windows of consecutive variables is presented. The algorithms have been fully integrated into the Berkeley and Carnegie Mellon BDD packages in such a way that the current variable order dynamically changes and is completely transparent to the user. Dynamic reordering significantly reduces the memory required for BDD-based verification algorithms, thus permitting the verification of significantly more complex systems than was previously possible. The algorithms exhibit a smooth tradeoff between CPU time and reduction in BDD size for almost all BDDs tested

Published in:

Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European

Date of Conference:

20-24 Sep 1993