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Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling

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2 Author(s)
Chandrasekaran, S. ; Dept. of Electron. & Comput. Eng., Sch. of Eng. & Design Brunei Univ., West London ; Amira, A.

A framework for power optimisation on FPGA based designs at various functional levels, and high level power estimation methodologies have been presented in this paper. Results obtained are very promising and the developed framework can be employed to power down the FPGA, estimate and model the power for other parameterisable IP cores

Published in:

Field Programmable Logic and Applications, 2006. FPL '06. International Conference on

Date of Conference:

28-30 Aug. 2006