Referenced Items are not available for this document.
A framework for power optimisation on FPGA based designs at various functional levels, and high level power estimation methodologies have been presented in this paper. Results obtained are very promising and the developed framework can be employed to power down the FPGA, estimate and model the power for other parameterisable IP cores
Published in:
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Date of Conference: 28-30 Aug. 2006
- Page(s):
- 1 - 2
- Print ISBN:
- 1-4244-0312-X
- INSPEC Accession Number:
- 9286619
- Conference Location :
- Madrid
- Digital Object Identifier :
- 10.1109/FPL.2006.311363
- Product Type:
- Conference Publications
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