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Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools

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3 Author(s)
Xin Wang ; Inst. of Digital & Comput. Syst., Tampere Univ. ; Ahonen, T. ; Nurmi, J.

An FPGA prototype of a four-node globally-asynchronous locally-synchronous network-on-chip is described. The network for global communication operates asynchronously at the link level and synchronously within a node. Two C-element control pipelines constitute the control logic for the asynchronous part. C-element and asynchronous arbiter realizations on FPGA using standard synchronous design tools are presented

Published in:

Field Programmable Logic and Applications, 2006. FPL '06. International Conference on

Date of Conference:

28-30 Aug. 2006