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A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design

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3 Author(s)
Alastair M. Smith ; Department of Electrical and Electronic Engineering, Imperial College London, email: ; George A. Constantinides ; Peter Y. K. Cheung

This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications, given a fixed silicon budget. We extend our previous mathematical programming framework by proposing a novel set of heuristics, capable of providing upper-bounds on the achievable reconfigurable-to-fixed-logic performance ratio. Moreover, we use linear-programming bounding procedures from the operations research community to provide lower-bounds on the same quantity. Our results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context, and indicate that only a minimal performance benefit can be achieved over Virtex II by re-organising the device floorplan, when using optimal technology mapping

Published in:

2006 International Conference on Field Programmable Logic and Applications

Date of Conference:

28-30 Aug. 2006