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Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm

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3 Author(s)
Qiang Liu ; Department of EEE, Imperial College London, London SW7 2AZ, email: qiang.liu2@imperial.ac.uk ; Konstantinos Masselos ; George A. Constantinides

Compilation of high level descriptions to field programmable gate array hardware forms a promising option for the efficient mapping of computationally intensive applications under tight development time constraints. In this paper data reuse exploration on top of an existing hardware compilation environment is discussed. The full search motion estimation algorithm for video processing is used as a test vehicle. The systematic approach adopted for the exploration of the data reuse space is described. Experimental results prove that the exploitation of data reuse may lead to more than 80% reduction of the execution time and up to 95% reduction of the off-chip memory accesses.

Published in:

2006 International Conference on Field Programmable Logic and Applications

Date of Conference:

28-30 Aug. 2006