By Topic

Modular Partitioning for Incremental Compilation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Mehrdad Eslami Dehkordi ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont. ; Brown, S.D. ; Borer, T.

This paper presents an automated partitioning strategy to divide a design into a set of partitions based on design hierarchy information. While the primary objective is to use these partitions in an incremental design flow for compile time reduction, the performance of the partitioned design should not be degraded after partitioning. Experimental results using the incremental design feature of Altera's Quartus tool show that our algorithm can generate partitioning solutions comparable with a set of manually partitioned industrial circuits and results in more than 50% compile time reduction

Published in:

Field Programmable Logic and Applications, 2006. FPL '06. International Conference on

Date of Conference:

28-30 Aug. 2006