By Topic

CMOS Multistage Preamplifier Design for High-Speed and High-Resolution Comparators

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Shirai, E. ; Semicond. Device Dev. Center, Canon Inc., Kanagawa

This brief describes a design technique for multistage preamplifiers of the type commonly used in high-performance comparators. Following the examination of multistage preamplifier responses in both the spectral and time domains, and a consideration 1/f noise attenuation in topologies employing offset storage capacitors, a procedure for optimizing both the number of stages and the offset storage capacitance is presented. As a demonstration vehicle, a comparator with a 13-Msample/s conversion rate and 200-muV minimum input resolution is designed for realization in a 0.4-mum CMOS technology under the constraint of a power dissipation of 250 muW when operating from a 2.5-V supply. In this design, the effective input signal is 33 muV for the minimum input resolution of 200 muV due to signal corruption from circuit noise and residual error from incomplete settling

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 2 )