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VMOS, UMOS structures simulation in micro and nano scale

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3 Author(s)
T. Kersys ; Department of Electronics Engineering, Kaunas University of Technology, Studentu str. 50, 51368 Kaunas, Lithuania. ; D. Andriukaitis ; R. Anilionis

VMOS, UMOS ("V"-groove-metal-oxide-silicon) transistors drain and gate are formed in the groove of "V" or "U" form. Expanding channel area, therefore VMOS and UMOS structures may be used in the power chips. Using VMOS, UMOS saves 40% free space than by using NMOS technology. Nanostructures dimensions are very small, so it is important to keep pn junction in a right depth, and in the all semiconductor manufacturing technological process. Analyzing influence to forming structure of each technological operation, mathematical simulation program SUPREM IV is used. VMOS and UMOS technological operation was simulated in micro and nano level

Published in:

2006 International Biennial Baltic Electronics Conference

Date of Conference:

2-4 Oct. 2006