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A Reconfigurable Simulation Framework for Financial Computation

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4 Author(s)
Jacob A. Bower ; Department of Computing, Imperial College, 180 Queen's Gate, London SW7 2AZ, UK. ; David B. Thomas ; Wayne Luk ; Oskar Mencer

This paper presents a framework for the acceleration of Monte-Carlo simulations using reconfigurable hardware. Discrete-time random walk simulations are widely used in the financial computation to calculate derivative prices and evaluate portfolio risk, but increases in model complexity and tighter time constraints now require large computer farms to meet operational demands. We present a model for accelerating such tasks with reconfigurable hardware, using an architecture that exploits parallelism at multiple levels, combining fine-grained pipelining, intra-device multi-threading and inter-device distributed processing. The architecture adopts a modular design approach, allowing components to be re-used across different applications, while also allowing automatic design space exploration to maximise performance within different devices. Using our framework, we implement two different discrete-time random walks representative of financial simulations and these show 71 times and 8 times speedup respectively when compared to a C++ software and SSE vectorised implementations

Published in:

2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)

Date of Conference:

Sept. 2006