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Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures

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4 Author(s)

Coarse-grained reconfigurable array architectures are currently focus of intensive research. They have already proven performance improvements and energy savings over traditional architectures. However, coarse-grained arrays vary widely in the number and characteristics of the processing elements and routing topologies used. This work presents a flexible mapping environment for design space exploration of coarse-grained, data-driven, reconfigurable array architectures. The mapping included in the environment presented in this paper takes advantage of Java and XML technologies to enable an efficient architectural tradeoff analysis. This approach does not focus on neither a specific mapping algorithm nor a specific architecture, but on an open environment where users can add their own mapping algorithms and architecture patterns. A genetic algorithm for placement is presented. A number of DSP benchmarks are used to explore a range of mesh architectures and to validate the approach. The experiments show a fast, scalable and flexible mapping environment to explore new mesh array patterns, homogeneous and heterogeneous architectures

Published in:

Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. IEEE International Conference on

Date of Conference:

Sept. 2006