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Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study

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3 Author(s)
Brown, A.R. ; Dept. of Electron. & Electr. Eng., Glasgow Univ. ; Roy, G. ; Asenov, A.

In this paper we present a 3D simulation study of the effect of Fermi level pinning along polysilicon gate grain boundaries on nano-MOSFET variability. Pinning of the Fermi level results in variations between devices depending on the random pattern of grain boundaries within the gate. We present a coherent 3D simulation methodology demonstrating the necessity of statistical simulations. As an illustration of our approach, we have carried out a statistical analysis of the variation in threshold voltage induced by polysilicon grain boundaries for a 30 nm MOSFET

Published in:

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Date of Conference:

19-21 Sept. 2006