Cross-wafer controlled interface layer thickness variation, and its application to SiO2 / high-κ stack characterisation

A technique has been developed to fabricate transistors using a continuously scaled 0-2.5 nm SiO
₂
interface layer between a silicon substrate and high-κ dielectric on a single wafer. Transistor results are promising with good mobility values and drive current. The slant etching process has no detrimental effect on the electrical characteristics of the Si/SiO
₂
interface. This technique provides a powerful tool to examine the effect of process variations on device performance. It has been used to demonstrate that reducing source/drain anneal temperature, from 1000degC to 700degC, results in a significant mobility degradation, for SiO
₂
interlayer thickness less than 1.0 nm. Above this thickness, the mobility and D
_IT
are relatively independent of anneal temperature