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LASER Anneal to Enable Ultimate CMOS Scaling with PMOS Band Edge Metal Gate/High-K Stacks

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11 Author(s)
Gilmer, D.C. ; Austin Silicon Technol. Solutions, Freescale Semicond. Inc., Austin, TX ; Schaeffer, J.K. ; Taylor, W.J. ; Spencer, G.
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For the first time, we report on the beneficial result for minimizing the activation thermal budget using LASER anneals with metal-oxide-gate-electrode/high-k dielectric MOSFETs. With LASER activation, EOT for PMOS conductive metal-oxide gated devices is reduced 4-5Aring compared to conventional RTP activation methods leading to more aggressive ultimate CMOS scaling when using a conductive metal-oxide for the PMOS gate electrode

Published in:

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Date of Conference:

19-21 Sept. 2006