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Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell

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6 Author(s)
Joshi, R. ; IBM T.J. Watson Res. Labs., Yorktown Heights, NY ; Kanj, R. ; Nassif, S. ; Plass, D.
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This paper describes the application of a novel variability-driven statistical analysis methodology to study the stability/performance of SRAM designs in 65nm PD/SOI technology. Our objective is to explore the design-yield space for wordline and bitline voltage assignments in dual supply SRAM while taking into consideration the impact of random process variations. Two possible scenarios are studied: namely wordline connected to the SRAM cell power supply, and wordline connected to the logic power supply. To the best of our knowledge this is the first time a fully statistical analysis is performed, and results are in excellent agreement with hardware measurements

Published in:

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Date of Conference:

19-21 Sept. 2006