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VDNROM: A Novel Four-Bits-Per-Cell Vertical Channel Dual-Nitride-Trapping-Layer ROM for High Density Flash Memory Applications

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9 Author(s)
Falong Zhou ; Inst. of Microelectron., Peking Univ., Beijing ; Yimao Cai ; Ru Huang ; Li, Yan
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A novel vertical channel nonvolatile memory cell with oxide-nitride-oxide-nitride-oxide (ONONO, dual nitride trapping layers) dielectrics stack is proposed and experimentally demonstrated for the first time. Compared with the conventional planar NROM cell, since the cell area of the proposed vertical structure is independent of the gate length, the VDNROM structure can relax the limitation of the gate length scaling, and can have high capability of cell area shrinking. The fabrication process of this VDNROM device is basically compatible with planar CMOS technology. The VDNROM cell can be programmed and erased by the hot carrier injection to the localized trapping dual-nitride-layers, so it can achieve a four physical bits storage capability each cell. The reliability behaviors including the cycling endurance and the bake retention at 150degC have also been investigated and show the acceptable characteristics. The experiment results verify the VDNROM cell as a good candidate for high-density applications

Published in:

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Date of Conference:

19-21 Sept. 2006