By Topic

CMOS Compatible Dual Metal Gate Integration with Successful Vth Adjustment on High-k HfTaON by High-Temperature Metal Intermixing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

12 Author(s)
C. Ren ; Silicon Nano Device Lab (SNDL), Dept. of ECE, National University of Singapore, Singapore 119260; Institute of Microelectronics (IME), Science Park II, Singapore 117685 ; D. S. H. Chan ; W. Y. Loh ; J. W. Peng
more authors

The paper reports a novel dual metal gate (MG) integration technique for gate-first CMOS process by intermixing (InM) of ultra-thin metal and metal nitride (MNx) films at high temperature together with source/drain (S/D) activation process. In this process, a thin (~2 nm) TaN buffer layer is used to prevent the gate dielectric being exposed during the metal etching process. Work function (WF) of TaN can be adjusted for NMOS/PMOS by intermixing of the TaN buffer layer with other metals on top of TaN during S/D activation. Prototype metal stacks of TaN/Tb/TaN (NMOS) and TaN/Ti/HfN (PMOS) have been integrated on a single wafer, with WF of 4.15 eV and 4.72 eV achieved, respectively. Successful Vth adjustment and good transistor characteristics are also demonstrated on HfTaON dielectric

Published in:

2006 European Solid-State Device Research Conference

Date of Conference:

19-21 Sept. 2006