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A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique

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6 Author(s)
Young-Deuk Jeon ; Electron. & Telecommun. Res. Inst., Daejeon ; Seung-Chul Lee ; Kwi-Dong Kim ; Jong-Kee Kwon
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This paper describes a 10-bit 20-MSample/s analog-to-digital converter (ADC) employing a multi-stage amplifier sharing scheme to reduce the power consumption and chip area at low supply voltages. The proposed scheme shares a multi-stage amplifier between a sample-and-hold amplifier and a first-stage multi-bit multiplying digital-to-analog converter by changing loop configurations of the amplifier. For further power and chip area reduction, the same resistor ladder is shared between the adjacent flash ADC blocks. The prototype ADC fabricated in a 0.13-¿m CMOS technology shows a signal-to-noise-and-distortion ratio of 56.0 dB and a spurious-free dynamic range of 68.7 dB with a 2-MHz sinusoidal input at 20 MSample/s. The ADC occupies 0.26 mm2 and dissipates 5 mW at a 1.2-V supply.

Published in:

Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European

Date of Conference:

Sept. 2006

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