Activation Technique for Sleep-Transistor Circuits for Reduced Power Supply Noise

Power gating is an effective leakage reduction technique with good scaling properties. The capability for a single cycle activation of large circuit blocks results as a consequence of sizing the sleep transistor for small delay degradation. However, in a system on chip environment this fast activation causes large current spikes and degrades the supply voltage of surrounding circuit blocks due to IR-drop and inductive voltage droop. To avoid timing errors in these blocks, a charge pump based activation technique is proposed and demonstrated experimentally. It is insensitive to process variations and can reduce the activation current to arbitrarily small values at the expense of an increased activation time. The capability for digital tuning allows for adaption of maximum activation current and latency to the system requirements. A monitor circuit tracks the virtual rail potential and indicates the end of the block activation.