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Embeded EEPROM Memory Achieving Lower Power - New design of EEPROM memory for RFID tag IC

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4 Author(s)
Liu Dong-Sheng ; Dept. of Electron. Sci. & Technol., Huazhong Univ. of Sci. & Technol., Wuhan ; Zou Xue-cheng ; Zhang Fan ; Deng Min

A 2-kb embedded EEPROM memory, operating over a wide voltage range (typically 2.5 V-5 V), was designed and fabricated using the SMIC 0.35-mum 2P3M CMOS embedded EEPROM process. The chip size is about 0.6 mm2. The method of adding control transistors improved the static power dissipation. The transient power consumption of the charge pump circuit was greatly reduced by using a slowly varying clock. The proposed SA using a voltage sensing method also significantly improved the read power dissipation. By employing these techniques, a low-power embedded EEPROM memory with 40 muA read current and 250 muA page write current was developed, that achieved much lower power than EEPROM memory designs reported in scientific journals or conferences. This EEPROM memory was used in the ISO/IEC 15693-compatible RFID tag IC project

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Circuits and Devices Magazine, IEEE  (Volume:22 ,  Issue: 6 )