By Topic

Design of Adiabatic SRAM Based on CTGAL Circuit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jun-Jun Yu ; Inst. of Circuits & Syst., Ningbo Univ. ; Peng-Jun Wang

A new adiabatic logic circuit adopting two-phase power clocks - clocked transmission gate adiabatic logic (CTGAL) circuit was presented. CTGAL circuit was used to design a novel adiabatic SRAM, and its bootstrapped NMOS transistors and CMOS-latch structure could recover the charge of large switching capacitances on word-lines, write bit-lines, sense amplified lines and address decoders in a fully adiabatic manner. Using the parameters of TSMC 0.25mum CMOS device, the adiabatic SRAM based on CTGAL circuit was simulated by HSPICE. The simulation results indicated that this SRAM had correct logic function and the character of clearly low power

Published in:

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Date of Conference:

23-26 Oct. 2006