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Cubic Packing with Various Candidates for 3D IC Design

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5 Author(s)
Yuchun Ma ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beiijng ; Zhuoyuan Li ; Xianlong Hong ; Cong, J.
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In this paper, we introduce various candidates for circuit blocks so that the floorplanner can dynamically choose the implementations of blocks to optimize the whole chip. Especially in 3D IC design, some components may occupy more than one layer, we propose a novel method to optimize the cubic packing with various candidates. Based on 3D-CBL (3-dimensional corner block list) representation, we can handle the layer number constraints heuristically and we guarantee the feasibility of the final results. Experimental results show that our algorithm is effective and efficient

Published in:
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Date of Conference: 23-26 Oct. 2006

Page(s):
2079 - 2081
E-ISBN :
1-4244-0161-5
Print ISBN:
1-4244-0160-7
INSPEC Accession Number:
9408779
Conference Location :
Shanghai
Digital Object Identifier :
10.1109/ICSICT.2006.306622
Product Type:
Conference Publications

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