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A Novel Parallel Processing Architecture for Deblocking Filter in H.264 Using Vertical MB Filtering Order

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2 Author(s)
Yue-Xi Zhao ; Dept. of Microelectron., Peking Univ., Beijing ; An-Ping Jiang

An efficient parallel processing method for deblocking filter design in H.264 video coding standard is presented in this paper. In order to reduce the memory reference and make the intermediate data reused as soon as possible, an advanced filtering order is taken, and read/write operation on external memory is executed in parallel with filtering computation. Furthermore, preloading operation is taken to reduce complexity of memory structure, and vertical MB processing order is used for improving the efficiency of intermediate data reuse. As a result, the processing cycles of the proposed architecture with single-port memory architecture is reduced by 80.5% compared with the advanced architecture of previous proposals

Published in:

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Date of Conference:

2006