Referenced Items are not available for this document.
In this paper, the VLSI hardware complexity for H.264 integer motion estimation is analyzed, several hardware-reduction techniques are investigated and a Sot-SAD-Tree VLSI structure based on SAD-Tree is proposed. Using this Sot-SAD-Tree structure, the whole data path width is reduced to 50%, and the H.264 encoder with large frame and complex motion vector can be VLSI implementation with acceptable hardware cost. Finally, a complete H.264 SDTV integer motion estimation VLSI architecture with 16times256 parallelism is designed and implemented
Published in:
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Date of Conference: 23-26 Oct. 2006
- Page(s):
- 2019 - 2021
- E-ISBN :
- 1-4244-0161-5
- Print ISBN:
- 1-4244-0160-7
- INSPEC Accession Number:
- 9408761
- Conference Location :
- Shanghai
- Digital Object Identifier :
- 10.1109/ICSICT.2006.306580
- Product Type:
- Conference Publications
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