By Topic

Efficient Optimization Methodology in Early-Stage Design of Mesh-structured On-Chip Power/Ground (P/G) Networks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Zu-ying Luo ; Dept. of Electron., Beijing Normal Univ.

Due to decreasing supply voltages and increasing power consumption of today's VLSI chips, IR drops on on-chip power/ground (P/G) grids have to be explicitly considered during floorplanning stage in the today's physical design flow. It is therefore very important to adjust the double-mesh P/G grids in the floorplanning for efficiently minimizing the worst-case IR drop subject to limited routing resource in early-stage P/G network design of high-end chips. In this paper, the author presented a novel feasible methodology to efficiently optimize the problem of mesh-structured center-bumped P/G grids under given routing resources. In Zhang, L-H and Luo, Z-Y, 2004, they have proposed the approximate current distribution (ACD) simulation method and the OS_SMACD optimization approach for early-stage single-level P/G meshes. In this work, a feasible theory is induced to directly compute the optimal solutions OS_DMACD for practical double-mesh P/G grids of high-end chips. Experimental results show that OS_DMACD matches very well with the exact counterparts inefficiently obtained with ICCG, which can leads to significant speedup in the today IR-drop aware floorplanning

Published in:

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

Date of Conference:

23-26 Oct. 2006