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Defect passivation and interface engineering for high-K gate dielectric device performance and reliability enhancement

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1 Author(s)
Hsing-huang Tseng ; Front End Processes Div., SEMATECH, Austin, TX

Using a fluorinated high-k/metal gate stack combined with a stress relieved pre-oxide (SRPO) pretreatment before high-k deposition, the authors show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern. The novel fluorinated gate stack device exceeds the PBTI and NBTI targets with sufficient margin and has electron mobility comparable to the best polySi/SiON device on bulk Si reported so far

Published in:

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

Date of Conference:

Oct. 2006