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A study of threshold voltage for poly-silicon thin film transistors

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3 Author(s)
Ming Tang ; Dept. Electr. Eng., National Chung Hsing Univ., Taichung ; Chang, S.T. ; Ho, C.S.

The paper presents a study of threshold voltage for poly-silicon TFTs through a designated experiment with several split conditions on the LDD implantation. Our results show that the abnormality of threshold voltage is caused by the effect of poly grain boundary trapping combining with the LDD condition along the channel edge region. In addition, PLN process is found to be another factor for the threshold voltage shift and variation. Theoretical interpretation by way of TCAD simulation is presented as well

Published in:
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Date of Conference: Oct. 2006

Page(s):
178 - 181
E-ISBN :
1-4244-0161-5
Print ISBN:
1-4244-0160-7
INSPEC Accession Number:
9398389
Conference Location :
Shanghai
Digital Object Identifier :
10.1109/ICSICT.2006.306131
Product Type:
Conference Publications

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