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A 12 bit, 2 V current-mode pipelined A/D converter using a digital CMOS process

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3 Author(s)
Ligang Zhang ; Crystal Semicond. Corp., Austin, TX, USA ; T. Sculley ; T. Fiez

The design of an A/D converter for the next generation of processes requiring lower supply voltages is explored through the design and implementation of a 12 bit converter in a 1.2 /spl mu/m digital CMOS process using a 2 V analog power supply. The resulting chip is 22.4 mm/sup 2/ and is presently being tested. It is expected to achieve a 1 MHz sampling rate with an analog power dissipation of 60 mW.<>

Published in:

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94  (Volume:5 )

Date of Conference:

May 30 1994-June 2 1994