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An algorithmic analog-to-digital converter with low ratio- and gain-sensitivities 4N-clock conversion cycle

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2 Author(s)
Chin, S.-Y. ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chung-Yu Wu, Ph.D.

This paper describes a new SC method to reduce the capacitor mismatching error and finite-gain error in an ADC. Through the use of switched-capacitor techniques, the proposed new ADC is insensitive to the capacitor-ratio accuracy as well as the finite gain and the offset voltage of the operational amplifiers. The switching error becomes the only major error source. Moreover, the cycle time for n-bit conversion is reduced to 4n-clock time. Both SWITCAP and HSpice simulations have been performed to verify the performance of the new ADC. It is shown that a 15-bit resolution at the sampling frequency of 20 KHz can be achieved when the capacitor ratios have a variation of 1% and the finite gain of the op amps is only 65 dB

Published in:

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on  (Volume:5 )

Date of Conference:

30 May-2 Jun 1994