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Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture

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2 Author(s)
Vijay, U.K. ; CEDTDept., IISc, Bangalore ; Bharadwaj, A.

A novel comparator architecture is proposed for speed operation in low voltage environment. Performance comparison with a conventional regenerative comparator shows a speed-up of 41%. The proposed comparator is embedded in a continuous time sigma-delta ADC so as to reduce the quantizer delay and hence minimizes the excess loop delay problem. A performance enhancement of 1dB in the dynamic range of the ADC is achieved with this new comparator. We have implemented this ADC in a standard single-poly 8-Metal 0.13 mum UMC process. The entire system operates at 1.2 V supply providing a dynamic range of 32 dB consuming 720 muW of power and occupies an area of 0.1 mm2.

Published in:

VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Date of Conference:

6-10 Jan. 2007