By Topic

Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jain, R. ; CoWare India Pvt Ltd, Noida ; Panda, P.R.

The discrete wavelet transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall power dissipation is dominated by read and write operations in the memory subsystem. The proposed architecture and computation sequence, called low-power block-scan, takes into account the EBCOT (embedded block coding with optimized truncation) code block size, which reduces the intermediate buffer requirement between the DWT and EBCOT modules. The impact of different memory subsystem optimization techniques on the overall memory power for 2D-DWT computation was modeled. The proposed model explores the different data access patterns, memory bank partitioning, and custom memory architectures to arrive at a power-efficient DWT architecture

Published in:

VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Date of Conference:

Jan. 2007