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Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan

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3 Author(s)
Kim T. Le ; University of Canberra, Australia ; Dong H. Baik ; Kewal K. Saluja

Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors

Published in:

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

Date of Conference:

6-10 Jan. 2007