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Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis

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3 Author(s)
Bansal, N. ; NEC Labs. America, Princeton, NJ ; Lahiri, K. ; Raghunathan, A.

Modern system-on-chips (SoCs) are often designed under stringent time to market constraints. Hence, they are realized by reusing a number of predesigned components (or IP blocks) that implement standard, yet critical functions. An important category of IP blocks are the so called infrastructure IP (IIP) blocks, which include interfaces to off chip memory, I/O devices, and peripherals, as well as hardware to provide DMA transfers, interrupts, timing, etc. IIP components are often responsible for a substantial portion of a SoC's power consumption, making it important to model and consider their effect in power aware SoC design. However, system level power analysis and optimization has, for the most part, focused on the processor, memory hierarchy, interconnect, and application specific hardware. Relatively little work has addressed modeling the power consumed by these infrastructure IP (IIP) components, or their impact on system level tradeoffs. This paper describes a systematic methodology to automatically generate power models for IIP components for use in system level power analysis and optimization tools. Our methodology starts with (i) a high level functional model of an IIP component designed for fast simulation, and (ii) a corresponding implementation model (RTL or gate level description), from which accurate power estimates can be obtained. It automatically generates an enhanced version of the high level functional model, which includes an accurate, yet efficient power model. This paper describes the key steps of the methodology, and presents techniques based on statistical analysis and symbolic regression to automate the most labor intensive steps. The proposed methodology has been applied to several commercial IIP designs, including ones from the Synopsys Design Ware library. The resulting power models produce estimates that are within 7% of gate level power analysis, while being several hundred times faster, making them highly suitable for system level pow- - er analysis. Moreover, the use of an automatic methodology drastically reduces the effort spent in power model development, from over a week to under an hour in some cases. The automatically generated models have been integrated into an inhouse system level power estimation framework. We demonstrate their utility in exploring system level design tradeoffs using an example SoC design

Published in:

VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Date of Conference:

6-10 Jan. 2007