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Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms

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3 Author(s)
V. R. Devanathan ; ASIC, Texas Instruments India Pvt. Ltd., Bangalore, India ; C. P. Ravikumar ; V. Kamakoti

A hierarchical or "divide-and-conquer" scan test methodology enables us to partition a large SoC into several partitions and perform design-for-testability (DFT) functions such as scan insertion, pattern generation, and pattern validation separately on individual partitions. Since the effort for DFT related tasks grows super-linearly with gate count, partitioning reduces the effort for DFT tasks. Further, test application can be divided into k + 1 modes, where k modes correspond to independent testing of the partitions and the (k + 1)th mode corresponds to a "residual" (or daisy) mode where faults that are not covered by the individual modes are considered. In reality, however, the daisy mode can be a killer and wipe out the benefits of divide-and-conquer testing. This is especially true for partitions that do not have test wrappers. In this paper, we take up the challenge of reducing the overhead of daisy mode in divide-and-conquer testing. By a careful analysis of the interactions between partitions, additional test modes are introduced to increase the coverage of glue logic, at the same time making sure that the number of scan cells involved in these "intermediate daisy modes" are minimal. We refer to this version of hierarchical scan testing as "quiet and optimized divide-and-conquer scan". Experimental results reveal that the proposed technique reduces the test time overhead of the conventional daisy mode by about 20times. In addition, the technique drastically reduces the switching activity in the daisy modes and hence reduces the test power

Published in:

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

Date of Conference:

Jan. 2007