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Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits

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1 Author(s)
Naidu, S.R. ; Magma Design Autom., Bangalore

This paper presents a pair of novel techniques to speed-up path-based Monte-Carlo simulation for statistical timing analysis of digital integrated circuits with no loss of accuracy. The presented techniques can be used in isolation or they could be used together. Both techniques can be readily implemented in any statistical timing framework. We compare our proposed Monte-Carlo simulation with traditional Monte-Carlo simulation in a rigorous framework and show that the new method is up to 2 times as efficient as the traditional method

Published in:

VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Date of Conference:

6-10 Jan. 2007

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