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Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits

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2 Author(s)
Sanghoan Chang ; Texas A&M University ; Gwan Choi

This paper presents a novel design approach for addressing the pressing problem of noise and signal integrity in high-speed circuits. The approach uses a combination of gate-level redundancy in form of a shadow circuit, exception handling, and retry to tolerate random and delay faults that are of increasing concern in modern circuits. An empirical evidence of the delay/random fault problem is developed and a scheme to press clocking frequency beyond traditional limit is presented. The results show that approximately 10% improvement in clocking frequency can be achieved with almost negligible performance penalty and 5%-20% area overhead for the benchmark circuits studied

Published in:

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

Date of Conference:

6-10 Jan. 2007