By Topic

Concurrent Optimization of Technology and Design for Nano CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Amerasekera, A. ; Texas Instrum.

As we move to 45nm and beyond, our ability to manage the need for increased integration together with the drive for higher system performance and lower power presents many challenges to technology and design. It has become no longer possible to consider technology advancement without considering the overall optimization of the transistor and circuit design for full entitlement together with the cost of the chip. This paper looks at the key challenges and technology discontinuities that we face as we move into the nano CMOS regime, and some of the approaches being developed to address them

Published in:

VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Date of Conference:

6-10 Jan. 2007