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High-speed and large noise margin tolerance E/D logic gates with LDD structure DMTs fabricated using selective RIE technology

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8 Author(s)

The authors describe a novel design concept for enhancement (E) and depletion (D) mode FET formation using i-AlGaAs/n-GaAs doped-channel hetero-MISFET (DMT) and a novel self-aligned gate process technology for submicrometer-gate DMT-LSIs based on E/D logic gates. 0.5-μm gate E-DMTs (D-DMTs) with a lightly doped drain (LDD) structure show an average Vt of 0.18 (-0.46) V, a Vt standard deviation of 22.6 (24.9) mV, and a maximum transconductance of 450 (300) mS/mm. The Vt shift is less than 50 mV with a decrease in gate length down to 0.5 μm. The gate forward turn-on voltage Vf is more than 0.9 V, i.e. about 1.6 times that for MESFETs. This superiority in V f, preserved in the high-temperature range, leads to an improvement in noise margin tolerance by a factor of three. In addition, 31-stage ring oscillators operate with a power consumption of 20 (1.0) mW/gate and a propagation delay of 4.8 (14.5) ps/gate. Circuit simulation based on the experimental data predicts 140 ps/gate and 1 mW/gate for DMT direct-coupled FET logic circuits under standard loading conditions. DMTs and the technology developed here are very attractive for realizing low-power and/or high speed LSIs

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Electron Devices, IEEE Transactions on  (Volume:36 ,  Issue: 10 )