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The Design And Implementation of the MC68851 Paged Memory Management Unit

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2 Author(s)
Cohen, B. ; Motorola Microprocessor Products Division ; Mcgarity, R.

Pipelining, microsequencer start-up in parallel with bus arbitration, and a fully associative translation cache enhanced the performance of this 32-bit memory management device.

Published in:

Micro, IEEE  (Volume:6 ,  Issue: 2 )

Date of Publication:

April 1986

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