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Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

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4 Author(s)
Celia Lopez-Ongil ; Departamento Tecnologia Electronica, Univ. Carlos III de Madrid ; Mario Garcia-Valderas ; Marta Portela-Garcia ; Luis Entrena

The appearance of nanometer technologies has produced a significant increase of integrated circuit sensitivity to radiation, making the occurrence of soft errors much more frequent, not only in applications working in harsh environments, like aerospace circuits, but also for applications working at the earth surface. Therefore, hardened circuits are currently demanded in many applications where fault tolerance was not a concern in the very near past. To this purpose, efficient hardness evaluation solutions are required to deal with the increasing size and complexity of modern VLSI circuits. In this paper, a very fast and cost effective solution for SEU sensitivity evaluation is presented. The proposed approach uses FPGA emulation in an autonomous manner to fully exploit the FPGA emulation speed. Three different techniques to implement it are proposed and analyzed. Experimental results show that the proposed Autonomous Emulation approach can reach execution rates higher than one million faults per second, providing a performance improvement of two orders of magnitude with respect to previous approaches. These rates give way to consider very large fault injection campaigns that were not possible in the past

Published in:

IEEE Transactions on Nuclear Science  (Volume:54 ,  Issue: 1 )