Referenced Items are not available for this document.
In this work, a methodology for the design of MOS current-mode logic frequency dividers is presented. A mix of hand calculations and circuit simulations is used to relate the power consumption and the frequency of operation. Each latch in the dividers is sized separately in order to minimize the overall power consumption. Furthermore, the effect on the power consumption of circuit parameters such as output swing and voltage gain of the input differential pair is analyzed in detail. The methodology has been applied to dividers by two and dividers by three with 50% output duty cycle
Published in:
Circuits and Systems I: Regular Papers, IEEE Transactions on
(Volume:54
,
Issue:
2
)
Date of Publication: Feb. 2007
- Page(s):
- 245 - 254
- ISSN :
- 1549-8328
- INSPEC Accession Number:
- 9306054
- Digital Object Identifier :
- 10.1109/TCSI.2006.885999
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 12 February 2007
- Issue Date :
- Feb. 2007
- Sponsored by :
- IEEE Circuits and Systems Society
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