Accurate modelling of the non-linear settling behaviour of current memory circuits

In switched current circuits, the clock frequency is limited by the maximum tolerable error. This paper presents a simple but accurate model for the settling behaviour of current memory cells. It is suitable for implementation in discrete-time simulators or synthesis tools, and requires far less computing time than a complete SPICE simulation, while giving comparable accuracy. The proposed model relies on a piece-wise linear description of the memory transistor's transconductance, and a precise modelling of the cell behaviour during the non-overlap of the sampling clocks. Both SPICE simulation and experimental results are compared to the new model.<
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