By Topic

Accurate modelling of the non-linear settling behaviour of current memory circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Moeneclaey, N. ; Dept. ISEN, CNRS, Lille, France ; Kaiser, A.

In switched current circuits, the clock frequency is limited by the maximum tolerable error. This paper presents a simple but accurate model for the settling behaviour of current memory cells. It is suitable for implementation in discrete-time simulators or synthesis tools, and requires far less computing time than a complete SPICE simulation, while giving comparable accuracy. The proposed model relies on a piece-wise linear description of the memory transistor's transconductance, and a precise modelling of the cell behaviour during the non-overlap of the sampling clocks. Both SPICE simulation and experimental results are compared to the new model

Published in:

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on  (Volume:1 )

Date of Conference:

30 May-2 Jun 1994