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A redefinable symbolic simulation technique to testability design rules checking

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4 Author(s)
M. Hirech ; Paris VI Univ., France ; O. Florent ; A. Greiner ; E. Rejouan

Symbolic simulation approach is well suited for VLSI design for testability (DFT) rules checking. Unfortunately the existing techniques are not extensible and therefore the verification tools based on them can not be parametrized to follow the evolution of rules. As a solution, a concept of symbolic simulator generator is proposed: both symbolic values and transfer functions of gates are redefinable to cope with different sets of rules and design methodologies

Published in:

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94  (Volume:1 )

Date of Conference:

30 May-2 Jun 1994