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ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

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3 Author(s)
Dutta, S. ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; Nag, S. ; Roy, K.

This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gate-level functional models and can be used for delay, area, and power optimization of CMOS combinational logic circuits in a VLSI design environment. The optimization technique is based on simulated annealing and considers the performance improvement of VLSI circuits by optimally sizing the transistors on the N most critical paths

Published in:

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on  (Volume:1 )

Date of Conference:

30 May-2 Jun 1994