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VLSI Implementation of Low Power High Throughput Low Density Parity Check Code Decoder for Optical Communication

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4 Author(s)
Kaushik Vaidyanathan ; Dept. of Electron. Eng., Anna Univ., Chennai ; Anusha Radhakrishnan ; Valli Sounthariya Kumar ; Kannan, K.

In this paper we propose a novel architecture with an adaptive approach to the existing partly parallel joint code and decoder design methodology for low density parity check (LDPC) codes. The low power and high throughput are achieved by an 'adaptive iteration controller', regulating the number of iterations required for error correction. We propose an architecture for a 2304 bit, rate-frac12, (3,6) regular LDPC code decoder which supports a symbol throughput of 216 Mbps and achieves a maximum BER of 10-6 at 2 dB over AWGN channel performing a maximum of 12 decoding iterations. We inspect the possibility of LDPC decoder serving as channel decoders for synchronous optical networks (SONET), 802.3an (10G Ethernet), DVB-S2 (digital video broadcast) and 802.16e (broadband wireless access). Cadence RTL Compiler has been used for synthesis at 90 nm and a special flow has been devised to predict and analyze performance in very deep sub-micrometer (vDSM)

Published in:

India Conference, 2006 Annual IEEE

Date of Conference:

Sept. 2006