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Parallel CRC Logic Optimization Algorithm for High Speed Communication Systems

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4 Author(s)
Hyunbean Yi ; Dept. of Comput. Sci. & Eng., Hanyang Univ., Seoul ; Jaehoon Song ; Sungju Park ; Changwon Park

This paper presents a new optimization algorithm for designing parallel cyclic redundancy check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on minimizing the logic level and finding XOR terms shared as many as possible. An Ethernet 32-bit CRC generator, which was designed and mapped to FPGA and a standard cell library, shows the superiority of our approach in reducing the delay and area overhead

Published in:

Communication systems, 2006. ICCS 2006. 10th IEEE Singapore International Conference on

Date of Conference:

Oct. 2006

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