Low Power Arithmetic Units for Video Processing Systems

Design of a low power multiply-and-accumulator (MAC) unit for video processing systems exploiting the similarity of neighboring pixels in video streams is presented in this paper. The proposed technique minimizes dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, one, repeated values or repeated bit combinations are detected and control signals are generated to bypass the data and to reuse the results in the MAC unit. It is observed that the proposed scheme helps to reduce operations and switching activities in the MAC unit up to 30% which results in lower power consumption with minimal hardware overhead