By Topic

Low Power Arithmetic Units for Video Processing Systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hau T. Ngo ; Computational Intelligence and Machine Vision Laboratory, Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA 23529. ; Vijayan K. Asari

Design of a low power multiply-and-accumulator (MAC) unit for video processing systems exploiting the similarity of neighboring pixels in video streams is presented in this paper. The proposed technique minimizes dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, one, repeated values or repeated bit combinations are detected and control signals are generated to bypass the data and to reuse the results in the MAC unit. It is observed that the proposed scheme helps to reduce operations and switching activities in the MAC unit up to 30% which results in lower power consumption with minimal hardware overhead

Published in:

2006 10th IEEE Singapore International Conference on Communication Systems

Date of Conference:

Oct. 2006