By Topic

Bi-Layer Systolic Architecture for Bit-Serial Implementation of Discrete Wavelet Transform

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Mohanty, B.K. ; Dept. of Electron. & Commun., Jaypee Inst. of Eng. & Technol., Raghogarh ; Meher, P.K.

In this paper, we present a bit-serial systolic architecture for computation of the discrete wavelet transform (DWT). The computations pertaining to the low-pass and high-pass filters of the recursive pyramid algorithm (RPA) are computed separately by two different layers in the proposed bi-layer structure. The structure is fully pipelined and requires a clocking period of only one full-adder delay. The hardware complexity of the proposed design is 58% of the existing bit-serial architecture up to 4-th level of decomposition with less than half of the computation time of the other

Published in:

Communication systems, 2006. ICCS 2006. 10th IEEE Singapore International Conference on

Date of Conference:

Oct. 2006