By Topic

A Reconfigurable RF Circuit Architecture for Dynamic Power Reduction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Kawazoe, D. ; Precision & Intell. Lab., Tokyo Inst. of Technol., Yokohama ; Sugawara, H. ; Ito, T. ; Okada, K.
more authors

This paper proposes a reconfigurable RF circuit architecture for dynamic power reduction. The architecture consists of RF circuits and a control circuit. The RF circuits can be reconfigured by bias voltages of transistors and variable passive devices, and the RF circuit block can also be switched dynamically. Analog RF circuits usually have redundant margin in circuit performance to compensate PVT variations, and it also causes redundant power consumption. The reconfigurable RF circuit can reduce power consumption by the dynamic reconfiguration, which compensates the performance margin. We demonstrate dynamic power reduction for opamp and LNA.

Published in:

TENCON 2005 2005 IEEE Region 10

Date of Conference:

21-24 Nov. 2005