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On-chip Test and Repair of Memories for Static and Dynamic Faults

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3 Author(s)
Sanjay K. Thakur ; Texas Instruments (India) Pvt. Ltd., Bangalore, India. Email: ; Rubin A. Parekhji ; A. N. Chandorkar

In addition to static faults, dynamic faults are increasingly important for high density embedded memories due to aggressive design rules and shrinking feature sizes. Not only is the test of these faults important, their repair is important too for devices where the yield loss due to memory fails is significant. Dynamic faults can impact one or more memory cells. In the case of the latter, it is also important to diagnose the cell causing the fault, and hence to be repaired. This paper describes an on-chip test and repair solution for static and dynamic faults in random access memories. The main contributions of this paper are three fold: (i) development of new algorithms for detection of static and dynamic faults, and for identification of faulty aggressor cells, (ii) extension of fault syndromes for diagnosis and location of aggressor cells, and (iii) development of an on-chip test, analysis and repair solution implementing these algorithms. It is shown how the proposed fault detection algorithms and redundancy analysis schemes are superior to existing ones for analysis time, hardware overhead, fault coverage and aggressor location capability

Published in:

2006 IEEE International Test Conference

Date of Conference:

Oct. 2006